Tomp
2002-04-22, 00:27:32
"The Die Size Advantage
Prescott may mark the end of an era where AMD could erode Intel market share as the result of Athlons much smaller die size compared to the Pentium 4 core. Fab capacity is the second hurdle (after processor performance) on the road to a bigger piece of the x86 processor market. A market good for few dozen billion dollars. The good news for AMD is that it's architects did a dual-processor-on-a-chip (CMP) version of Sledgehammer. This Hammer version may well turn out to be AMD's main stream processor at the 90 nm processor node. Two Hammer cores together with 1 Megabyte L2 cache would consume something like 95 square millimeters at the 90 nm process node. Smaller then its current smallest processor, the Duron that has something like 106 mm2 but larger than the projections for Prescott which are in order of 80 mm2"
Das hab ich auf http://www.chip-architect.com/news/2002_04_16_Prescott_Prospects.html#Intel versus AMD
gefunden. Hat AMD nicht mal gesagt, dass das gar nicht mit dem Hammer möglich wäre? Oder haben sie damit gemeint, dass das nur in 130nm nicht möglich wäre? Wäre auf jeden Fall geil, wenn auch wahrscheinlich für einen Normalsterblichen unerschwinglich.
Prescott may mark the end of an era where AMD could erode Intel market share as the result of Athlons much smaller die size compared to the Pentium 4 core. Fab capacity is the second hurdle (after processor performance) on the road to a bigger piece of the x86 processor market. A market good for few dozen billion dollars. The good news for AMD is that it's architects did a dual-processor-on-a-chip (CMP) version of Sledgehammer. This Hammer version may well turn out to be AMD's main stream processor at the 90 nm processor node. Two Hammer cores together with 1 Megabyte L2 cache would consume something like 95 square millimeters at the 90 nm process node. Smaller then its current smallest processor, the Duron that has something like 106 mm2 but larger than the projections for Prescott which are in order of 80 mm2"
Das hab ich auf http://www.chip-architect.com/news/2002_04_16_Prescott_Prospects.html#Intel versus AMD
gefunden. Hat AMD nicht mal gesagt, dass das gar nicht mit dem Hammer möglich wäre? Oder haben sie damit gemeint, dass das nur in 130nm nicht möglich wäre? Wäre auf jeden Fall geil, wenn auch wahrscheinlich für einen Normalsterblichen unerschwinglich.