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2005-04-18, 20:47:01
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By attentively studying the behavior of a Dual Core Athlon 64, we realized that a very interesting characteristic of the upcoming Desktop Dual Core chip from AMD was hidden. In fact, if the K8 marchitecture cannot support the Intel's HyperThreading (HT) technology, it seems that the CPUID registers of the processor are not of this opinion. If we carefully study the response to instruction CPUID with EAX = 1, we obtain the following values:
Athlon 64 Simple Core - CPUID (EAX = 1)
Hex (EDX) : 0x078bfbff
Bin (EDX) : 0b00000111100010111111101111111111
Hex (EBX) : 0x00000800
Athlon 64 Dual Core - CPUID (EAX = 1)
Hex (EDX) : 0x178bfbff
Bin (EDX) : 0b00010111100010111111101111111111
Hex (EBX) : 0x00020800
The bit 28 in register EDX (which is emphasized in red here) corresponds to the support of HyperThreading. However, we can see clearly that this bit is now set to 1 whereas it was to 0 for a standard, Single Core, Athlon 64. In the same way, the bits [23:16] of register EBX, which indicate the number of logicals CPU supported on Intel CPUs with Hyperthreading enabled, are also set to "2" in the case of a DC Athlon 64.
So, It seems that AMD chose to activate the "HyperThreading" bit on those Athlon 64 Desktop CPUs in order to profit from optimizations already done by many programmers for HyperThreading technology. This will make possible for those upcoming Athlon 64 Dual Core to also benefit from work already carried out. For now, we do not know yet if the Dual Core Opterons will also have this bit active.
x86-secret.fr (http://www.x86-secret.com/?option=newsd&nid=871)
Spekulationen dazu startete schon diese AMD-Info:
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_kernel_summit_08_RB.pdf
By attentively studying the behavior of a Dual Core Athlon 64, we realized that a very interesting characteristic of the upcoming Desktop Dual Core chip from AMD was hidden. In fact, if the K8 marchitecture cannot support the Intel's HyperThreading (HT) technology, it seems that the CPUID registers of the processor are not of this opinion. If we carefully study the response to instruction CPUID with EAX = 1, we obtain the following values:
Athlon 64 Simple Core - CPUID (EAX = 1)
Hex (EDX) : 0x078bfbff
Bin (EDX) : 0b00000111100010111111101111111111
Hex (EBX) : 0x00000800
Athlon 64 Dual Core - CPUID (EAX = 1)
Hex (EDX) : 0x178bfbff
Bin (EDX) : 0b00010111100010111111101111111111
Hex (EBX) : 0x00020800
The bit 28 in register EDX (which is emphasized in red here) corresponds to the support of HyperThreading. However, we can see clearly that this bit is now set to 1 whereas it was to 0 for a standard, Single Core, Athlon 64. In the same way, the bits [23:16] of register EBX, which indicate the number of logicals CPU supported on Intel CPUs with Hyperthreading enabled, are also set to "2" in the case of a DC Athlon 64.
So, It seems that AMD chose to activate the "HyperThreading" bit on those Athlon 64 Desktop CPUs in order to profit from optimizations already done by many programmers for HyperThreading technology. This will make possible for those upcoming Athlon 64 Dual Core to also benefit from work already carried out. For now, we do not know yet if the Dual Core Opterons will also have this bit active.
x86-secret.fr (http://www.x86-secret.com/?option=newsd&nid=871)
Spekulationen dazu startete schon diese AMD-Info:
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_kernel_summit_08_RB.pdf