Naomi
2002-07-25, 12:18:02
Bei Beyond3D (http://www.beyond3d.com/forum/viewtopic.php?t=1790) aufgeschnappt:
I've been corresponding with NVIDIA the last few days on the Siggraph 2002 presentations. Here's what they had to say:
1. It will be marketed as the first Cinematic Shading GPU
2. Pixel shaders can be 1024 instructions in a PASS . Of course you can multipass, but the program instruction length is considered a pass
ALU functions for the Pixel Shader: ADD,DP3, DP4, LRP, MOV, MAD, SUB, X2D (add and multiply) ,TEX, TXD, TXP (texturing), COS, EX2, FLR, FRC, LG2, POW< RCP, RSQ, SIN (math instructions), SEQ, SLF, SGR, SGT, SLE, SNE, STR (set "on" instructions), DST, LIT, RFL (graphics), MIN, MAX (minimum , maximum) PK2H , PK2US, PK4B, PK4UB, PK4UBG (pack) UP2H, UP2US, UP4B, UP4UB, UP4UBG(unpack) , Kill (kill)
3. Vertex Shaders programs can be 65,536 instructions in length with the loops branches etc , it's also considered one pass .
Vertex Shader Instructions: ARL (4 component A0 and A1, ARR rounding instruction instead of truncating like ARL, BRA , CAL, RET (branchching instructions) COS , SIN (high precision trigonometric functions), FLR, FRC (floor and fractions of floating point values), EX2 , LG2 (high precision exponentiation and logarithym function), ARAm SEQ, SFL, SGT, SLE, SNE, STR, SSG
4. .13 micron
5. NVIDIA said fall part in June , and I've heard nothing from them that changes that outlook . despite the rumors.
6. NVIDIA will be using a form of DDR2 memory . This is CONFIRMED information. What clockspeeds , what bit interface, or memory bandwidth I
cannot confirm at this time
7. 12bit fixed point (sorry for confusion), 16bit 32bit float formats supported
8.16 textures per pixel ala DX9.
9. 16 texture units I cannot at this time confirm the configuration of those 16 units but they are there
10. John Carmack quote in it's entirety: Nvidia is the first of the consumer graphics companies to firmly understand what is going to be happening with the convergence of consumer realtime and professional offline rendering. The architectural decision in the NV30 to allow full floating point precision all the way to the framebuffer and texture fetch, instead of just in internal paths, is a good example of far sighted planning. It has been obvious to me for some time how things are going to come together, but Nvidia has made moves on both the technical and company strategic fronts that are going to accelerate my timetable over my original estimations
My current work on Doom is designed around what was possible on the original Geforce, and reaches an optimal impliementation on the NV30. My next generation of work is designed around what is made possible on the NV30.
11. NV30 and DX9 schedules are now aligned. This may change if Microsoft delays DX9 , but not the other way around.
12. DX9 shift from bandwidth to computation. Pixel Shading is not pixel filling
I've been corresponding with NVIDIA the last few days on the Siggraph 2002 presentations. Here's what they had to say:
1. It will be marketed as the first Cinematic Shading GPU
2. Pixel shaders can be 1024 instructions in a PASS . Of course you can multipass, but the program instruction length is considered a pass
ALU functions for the Pixel Shader: ADD,DP3, DP4, LRP, MOV, MAD, SUB, X2D (add and multiply) ,TEX, TXD, TXP (texturing), COS, EX2, FLR, FRC, LG2, POW< RCP, RSQ, SIN (math instructions), SEQ, SLF, SGR, SGT, SLE, SNE, STR (set "on" instructions), DST, LIT, RFL (graphics), MIN, MAX (minimum , maximum) PK2H , PK2US, PK4B, PK4UB, PK4UBG (pack) UP2H, UP2US, UP4B, UP4UB, UP4UBG(unpack) , Kill (kill)
3. Vertex Shaders programs can be 65,536 instructions in length with the loops branches etc , it's also considered one pass .
Vertex Shader Instructions: ARL (4 component A0 and A1, ARR rounding instruction instead of truncating like ARL, BRA , CAL, RET (branchching instructions) COS , SIN (high precision trigonometric functions), FLR, FRC (floor and fractions of floating point values), EX2 , LG2 (high precision exponentiation and logarithym function), ARAm SEQ, SFL, SGT, SLE, SNE, STR, SSG
4. .13 micron
5. NVIDIA said fall part in June , and I've heard nothing from them that changes that outlook . despite the rumors.
6. NVIDIA will be using a form of DDR2 memory . This is CONFIRMED information. What clockspeeds , what bit interface, or memory bandwidth I
cannot confirm at this time
7. 12bit fixed point (sorry for confusion), 16bit 32bit float formats supported
8.16 textures per pixel ala DX9.
9. 16 texture units I cannot at this time confirm the configuration of those 16 units but they are there
10. John Carmack quote in it's entirety: Nvidia is the first of the consumer graphics companies to firmly understand what is going to be happening with the convergence of consumer realtime and professional offline rendering. The architectural decision in the NV30 to allow full floating point precision all the way to the framebuffer and texture fetch, instead of just in internal paths, is a good example of far sighted planning. It has been obvious to me for some time how things are going to come together, but Nvidia has made moves on both the technical and company strategic fronts that are going to accelerate my timetable over my original estimations
My current work on Doom is designed around what was possible on the original Geforce, and reaches an optimal impliementation on the NV30. My next generation of work is designed around what is made possible on the NV30.
11. NV30 and DX9 schedules are now aligned. This may change if Microsoft delays DX9 , but not the other way around.
12. DX9 shift from bandwidth to computation. Pixel Shading is not pixel filling