Die Technik des Centrinos im Stromsparen

Ich weiss nicht, ob dies schon erwähnt wurde.

Hier wird ausführlich erklärt, was alles beim Pentium-M gemacht worden ist, um es sparsam zu machen. Es ist ziemlich ausführlich, deswegen nur Ausschnitte:

http://www.intel.com/technology/itj/...iss2_art03.pdf

Zitat:

Trading Performance For Power

Maximizing Performance at Given Thermal Constraints
we replaced the criterion “Maximizing performance at given thermal constraints” with: “Maximizing performance at a given power envelope"

Minimizing Energy Per Task

Reducing the Number of Instructions Per Task

Reducing the Number of Micro-ops Per Instruction

Reducing the Number of Transistor Switches Per Micro-op

Reducing the Amount of Energy Per Transistor Switch
...
Static Power
The power consumed by a processor consists of active power (used to switch transistors) and static power (leakage of transistors under voltage). In this paper we focus mainly on active power reduction, but it is worth mentioning how the Intel Pentium M processor also reduces static power consumption.
The static power is roughly a function of the number of transistors, their type, the operating voltage, and the die temperature. The Pentium M processor reduces static power by several means:
* Low-leakage devices. The processor’s 1MB power managed L2 cache, which contains roughly twothirds of the transistors in the processor, is built with low-leaking transistors. Low-leaking transistors are somewhat slower, thus slightly increasing the cache access latency, but the significant power saved justifies the small performance loss.
* Enhanced Intel SpeedStep technology. This advanced technology significantly reduces the processor voltage (and temperature), hence leakage
power, when processor activity is low.

POWER-AWARE FEATURES
The following sections describe several of the Intel Pentium M processor’s power-aware features. These features cover all the above-mentioned strategies:
• Reducing the number of instructions per task: advanced branch prediction.
• Reducing the number of micro-ops per instruction: micro-ops fusion and dedicated stack engine.
• Reducing the number of transistor switches per micro-op: the Intel Pentium M processor bus and various lower-level optimizations.
• Reducing the amount of energy per transistor switch: Intel SpeedStep technology.

http://www.intel.com/technology/itj/...ol09_art05.pdf
Hier ist die ganze Centrino Plattform erklärt.

Zitat:

2 MB Power-Optimized L2 Cache
The L2 cache is one of the most effective business productivity per watt enhancements offered by mobile processors today. The second-generation Intel Pentium M processor offers an unprecedented 2 MB, low-power, lowlatency L2 cache to efficiently tackle the growing working sets of present and future applications. The effect of on-die cache is to reduce the number of cycles wasted while waiting on memory. Not surprisingly, the percent
performance impact of this grows with increasing processor frequency. When operating at the maximum performance level tasks get done sooner allowing the entire system to return to a low-power state. Power is also conserved while in the adaptive state, a Windows XP Power Management Policy, which allows the processor to switch voltage and frequency dynamically to address
processor demand. Maximizing the potential of each intermediate-level performance point reduces the likelihood of crossing the utilization threshold that initiates a jump to the next frequency. This has a linear effect on power, due to frequency, and a square effect due to voltage (P∝cfv2) and corresponding voltage level, which further reduces power demands.
The performance/power benefits of a larger L2 cache vary depending on the workload. Office productivity usage models (MS Word, Excel, Virus Scan, etc.) typically have large data sets that force lots of off-chip accesses to
system memory; a larger L2 cache is definitely a plus in such an application environment.

Advanced Tight Loop Execution
The processor recognizes even the smallest opportunity to apply clever solutions to increase performance while reducing power: for example, when a small well-behaved loop is found to be contained within the Instruction Length Decode Queue, power is conserved by stalling the Instruction Fetch Unit and running code from the Prefetch Buffer. As the loop characteristics are well understood, the Branch Prediction Unit can be powered down saving even more power.

Das ganze Komplett:
http://www.intel.com/technology/itj/...ol09_iss01.pdf

Insgesamt kann man sagen, dass Intel alle Möglichkeiten ausnutzt, um den Prozessor Strom zu sparen.

Zitat:

Insgesamt kann man sagen, dass Intel alle Möglichkeiten ausnutzt, um den Prozessor Strom zu sparen.

Du hast offensichtlich noch nie etwas von Transmetas Long Run/Long Run 2 gehört ...

Intel hat zwar viel Stromspartechnik eingebaut, aber da ist immer noch eine Steigerung drin ...

Und SOI nutzt Intel derzeit nicht ... man kann daher sagen, dass Intel eben nicht alle Möglichkeiten nutzt ... (wer macht das schon).

[GloomY]

Ja, ich kannte den Artikel schon. Aber nichts desto trotz ist er interessant.

Bei den Leckströmen hat AMD mit SOI wohl einen Vorteil, während der Prozessorcore an sich bei Intels PentiumM weniger verbraucht. Alleine die drei Decoder des K7/K8 geben konstant eine gute Wärmemenge ab.